The present invention relates generally to complimentary metal oxide field effect transistors, electrically alterable read only memories and more specifically to such a memory incorporating bipolar transistors in emitter follower configurations.
Previous attempts to fabricate EAROM (Electrically Alterable Read Only Memory) devices have been limited by the thermal characteristics of the amorphous material. Since amorphous material degradation occurs at temperatures around 140.degree.-150.degree. C., the power dissipated by device (e.g. a 1K EAROM) must be kept small. If, for example, a 1K EAROM device was designed to dissipate a nominal power of 500 milliwatts and be packaged in a conventional CERDIP package, the die temperature would be as follows: T.sub.A (ambient temperature)+[.theta..sub.JA (junction to air thermal impedance) .times.P.sub.D (device power dissipation)]. For a conventional industrial operating temperature of 75.degree. C. and a conventional .theta..sub.JA of 80.degree. C./watt, the die temperature would be 115.degree. C. For a military operating temperature of 125.degree. C., the die temperature would be 165.degree. C.
In order to provide devices which can operate up to 125.degree. C., very elaborate packaging schemes (e.g., liquid cooled) have been employed from reducing .theta..sub.JA. Reduction of .theta..sub.JA to the range of 5.degree.-10.degree. C./watt has been achieved. This method has been successful but is extremely expensive.
Another method used for reducing the die temperature has been to reduce the device's power dissipation. For a device power dissipation of 100 milliwatts, an operating temperature of 125.degree. C. and a conventional CERDIP package, a die temperature of 133.degree. C. could be achieved. This reduction in power is viable but is very restrictive with respect to achievable speeds. Whereas a speed of 40-50 nanoseconds for a 1K EAROM could be achieved at a power level of 500 milliwatts nominal, the speed would be degraded to 150-200 nanoseconds at a power level of 100 milliwatts.
In order to provide amorphous material elements which have the capability of operating at high temperatures (e.g., 125.degree. C.), high threshold devices (e.g., 10-15 V) have been employed. In memory arrays where these elements have been used, either collector-base or Schottky diodes have been used due to component breakdown characteristics. The use of these diodes requires that the memory array be isolated, and hence, the achievable memory array size is limited. NPN transistors in an emitter follower configuration do not require surface area for isolation, thereby increasing density, but the low emitter to base breakdown voltage (generally 7 volts) prevents their use with high threshold devices.
The use of field effect transistors reduces power consumption, but they are very slow and their signal capacity is a function of their size. Bipolar transistors are capable of operating quickly and have a far greater signal capacity per unit area than field effect transistors, but they consume substantially greater power. Also bipolar transistors consume static power. The use of emitter followers in CMOS buffers has been described in the prior art, but these buffers generally consume static power.
Thus there exists a need for an EAROM which can satisfy the interrelationship between achievable speed, power, density and operating temperature without the requirement of exotic packaging schemes.